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Level-sensitive scan design
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Level-sensitive scan design : ウィキペディア英語版
Level-sensitive scan design

Level-sensitive scan design (LSSD) is part of an integrated circuit manufacturing test process. It is a DFT scan design method which uses separate system and scan clocks to distinguish between normal and test mode. Latches are used in pairs, each has a normal data input, data output and clock for system operation. For test operation, the two latches form a master/slave pair with one scan input, one scan output and non-overlapping scan clocks A and B which are held low during system operation but cause the scan data to be latched when pulsed high during scan.


抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)
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